1. Field of the Invention
The present invention relates to a memory system including a semiconductor memory, such as a DRAM, and a control method for the same.
2. Description of the Related Art
As this type of memory system, there is one disclosed in Japanese Unexamined Patent Publication No. 2001-256772 (hereinafter referred to as “quoted example 1”). In quoted example 1, a clock signal supplied from a memory controller MC to each module is reproduced and buffered through a PLL circuit on the module before it is distributed to each DRAM on the module. Meanwhile, an address and command signal is buffered by a buffer on each module before it is distributed to each DRAM. A data signal is supplied from the MC to the DRAMs on each module in parallel.
Quoted example 1 discloses a topology in which a data line on each module is not branched with respect to a data bus on a motherboard. This enables the operating frequency of a signal to be increased.
However, quoted example 1 merely discloses a wiring configuration on a module and does not at all refers to synchronizing the timings of address command signals and data signals with clock signals. Hence, it is impossible to analogize the timing relationship among the address command signals, the data signals and the clock signals, and also impossible to analogize any specific configuration for transferring address command signals and data signals to and from the DRAMs by utilizing the timing relationship.
Especially when operating a memory system at high frequencies, it is important to accomplish clock synchronization for transferring signals without a timing loss in addition to achieving improved signal quality. In the case of quoted example 1, the address signals, the command signals and the clock signals are all buffered on the modules, so that the signal timings at the DRAM ends depend on the characteristics of the individual buffering devices, thus leading to timing mismatches. Furthermore, the topologies of the signal lines for the data signals and the clock signals are completely different. As a result, since the signal timings are also different, how to match the data signals to the clock signals in the DRAMs becomes an important assignment.
The applicant has previously filed Japanese Patent Application No. 2001-236759 (hereinafter referred to as “quoted example 2”). Quoted example 2 discloses a memory system shown in FIG. 59. As illustrated, for each bundle of data lines 1021, 1022, 1023 and 1024 for transferring data signals, clock signal lines 1031, 1032, 1033 and 1034 associated or matched with the bundles 1021, 1022, 1023 and 1024 are connected such that they extend from the memory controller MC to the DRAMS of the modules. This configuration does not pose any problem with matching timings with the clock signals as long as the transfer of the data signals is concerned.
However, it is required to generate clock signals for each bundle of data signals on the system, and as the number of the bundles of data signals increases, the number of clock signals increases and the frequencies of data signals and clock signals increase, the problem of radiant noises may occur.
Furthermore, in the memory system shown in FIG. 59, the lines are branched, although command signals and address signals (hereinafter generically referred to as “command/address signals”) are not buffered in the modules. This makes it difficult to accomplish operation at high frequencies. In addition, quoted example 2 has disclosed the configuration in which each module is provided with a buffer for buffering command/address signals. It is necessary, however, to increase the number of clock signals for each bundle of data signals. Hence, it is considered inevitable for radiant noises to occur at high frequencies, as mentioned above.